Contact delay and self-destruct circuit

ABSTRACT

A circuit for providing a predetermined time delay after missile impact before detonation, and a self-destruct system controlled by the missile&#39;&#39;s operation. The circuit utilizes a quad inverter fed by the self-destruct system and the contact delay system, in parallel, driving a firing system. The contact delay system is basically a one-shot multivibrator, utilizing pulses from piezoelectric crystals as inputs, and having an RC timing circuit to trigger the firing system. The self-destruct system utilizes a reduced voltage resulting from an extinquished gas generator to trigger the firing system. The firing system has an SCR gate triggered by the quad inverter output.

Manning States Patent [1 1 451 Jan. 28, 19,75

-[22] Filed:

1 1 CONTACT DELAY AND SELF-DESTRUCT CIRCUIT [75] inventor: Larry G.Manning, China Lake,

Calif.

[73] Assignee: United States of America as represented by the Secretaryof the Navy, Washington, D.C.

May 14, 1970 [21] Appl. No.: 48,589

3,571,609 3/1971 Knudson 102/702 X I Primary Examiner-Benjamin A.Borchelt Assistant Examiner-C. T. Jordan Attorney, Agent, or Firm-R. S.Sciasciu; Roy Miller;- Robert W. Adams [57] ABSTRACT A circuit forproviding a predetermined time delay after missile impact beforedetonation, and a selfdestruct system controlled by the missile'soperation.

. The circuit utilizes a quad inverter fed by the selfdestruct systemand the contact delay system, in paralle1, driving a firing system. Thecontact delay system is basically a one-shot multivibrator, utilizingpulses from piezoelectric crystals as inputs, and having an RC timingcircuit to trigger the firing system. The selfdestruct system utilizes areduced voltage resulting from an extinquished gas generator to triggerthe firing system. The firing system has an SCR gate triggered by thequad inverter output.

7 Claims, 5 Drawing Figures "l'ARG ET k DETECTION 84 ER DEVICE OUTPUT GEFIRING CIRCUIT 3,453,496 1/1969 3,559,582 2/1971 3,571,605 3/1971 Dobsonet a1 102/702 X I? su| Y PL SELF- voLTAeE DESTRUCT CIRCUIT, I g

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22 INPUT st 24 CONTACT DELAY IL CIRCUIT 'PATEMIH] W628 I975 SHEET 10! 2.PDnE-DO Fm muzmmmmwm M Mm mw 5 KW FMY mN L Mm Mm MM CONTACT DELAY ANDSELF-DESTRUCT CIRCUIT GOVERNMENT INTEREST The invention described hereinmay be manufactured and used by or for the Government of the UnitedStates of America for governmental purposes without the payment of anyroyalties thereon or therefor.

BACKGROUND OF THE INVENTION The invention relates to the field ofmissile fuzing systems and, in particular, to the missiles hit and missmodes of operation.

Missile fuzing devices, prior to the present invention. gave a directpulse to the target detecting device, and fired upon impact with nodelay in time. The contact trigger circuits utilize transformercoupling, Shockley diodes and a relatively unregulated power supply.Inherent problems with the circuits are that Shockley diodes aredifficult to obtain, and missile warhead misfiring caused by circuittransients can occur due to the relatively unregulated power supply andtransformer coupling.

SUMMARY OF THE INVENTION The contact delay system utilizes readilyavailable components, no magnetic components and a well regulated powersupply. After the missile experiences contact with the target a timedelay, controllable by the selection of one resistor and one capacitor,prevents the circuit from delivering a destruct pulse to the targetdetection device firing circuit until after a predetermined time. hasexpired- The self-destruct system takes advantage of a reduced-voltagesupply caused by a reduction in the revolutions per minute of themissile turbo-generator, resulting from the lack of fuel in the missilegas generator, to provide a trigger pulse to the firing circuit. Thetarget detection device firing circuit was designed to allow broadsilicon controlled rectifier selection without reducing effectiveness.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a block diagram of thecomplete circuit;

FIG. 2 is a schematic diagram of the complete circuit;

FIG. 3 is a schematic diagram of the contact delay circuit;

FIG. 4 is a schematic diagram of the self-destruct circuit; and

FIG. 5 is a schematic diagram of the target detection device firingcircuit.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIGS. 1 and 2wherein the contact delay and self-destruct circuit consists of acontact delay circuit 10, a self-destruct circuit 12, a quad inverterdriver stage 14, and a target detection device firing circuit 16; Thecontact delay circuit 10, the selfdestruct circuit 12, and the targetdetection device firing circuit 16 are shown individually in FIGS. 3, 4and 5, and are not shown individually on FIG. 2 becausecertaincomponents are shared by two or more of the circuits.

Symbol Component Value or type 14 Quad inverter Motorola MC 927 G 20(Supply Voltage) +25 volts 26 Resistor (as required) 28 Resistor (asrequired) 30 Resistor 20 Kilohm 32 Resistor (1.8 Kilohm 34 Diode 1N751A36 Capacitor l microfarad, 20 volt 38 Resistor 820 ohm 4O Transistor2N929 42 Capacitor 0.1 microfarad 44 Resistor 430 ohm, 3 watt 46 DiodelN7-SOA, 4.7 vol! 48 Resistor 10 Kilohm 50 Diode 1N753A, 6.2 volt 52Resistor 2 Kilohm 54 Resistor 1.2l Kilohm, 1%, %watt 56 Capacitor lmicrofarad 58 Capacitor 0.1 microfarad 60 Resistor 2 Kilohm 62 Resistor1.5 Kilohm 64 Diode 1N973B, 33 volt 66 Diode lNo45 68 Resistor 221Kilohm, 1%, Vs watt 70 Diode 1N645 72 Silicon Controlled 2N1 874A 74Resistor 470 Kilohm, 1%

76 Resistor 33 Kilohm 78 Capacitor l0 microtfarad, volt 80 Resistor lKilohm 82 (TDD reference volts voltage) Referring now to FIG. 3 whichshows the contact delay portion 10 of FIGS. 1 and 2. The circuit isbasically a one-shot multivibrator which is held on by the charge timeof resistor 54 and capacitor 56. A quad inverter 14 is used to developthe one-shot circuit. Transistor 40 is employed in the input circuit asa pulse inverter and crystal isolation stage, and provides a high levelof rejection to noise on the missile supply line 20. The crystals, orany other means desired for providing inputs 22 and 24, are loaded bythe as-required resistors 26 and 28. in series with the parallelcombination of resistor 30, diode 34, and the input impedance oftransistor 40. This loading dampens the crystal output and reducesringing. The switching sensitivity of the input circuit is establishedby selecting the desired value of the as-required resistors 26 and 28.

The final transistor96 in the quad inverter 14 acts as a gate driver andtransfers a positive pulse through diode 66 to the silicon controlledrectifier gate (SCR) 72. This pulse is of sufficient amplitude to fire"the SCR 72 over the design temperature range.

The timing of the circuit is described by equation l below.

t, charge time of capacitor 56 to voltage e,

R timing resistor 54 C timing capacitor 56 e final voltage required toswitch transistor 94 e, transistor 94 base voltage at t E supply voltsat pin 10 of quad inverter 14 K 1.15 This equation maps the chargingrate of capacitor 56 immediately after transistor 90 is switchedon.

The total circuit delay can be computed by summing t, and the inherentcontact crystal delay.

The operation is as follows: a negative pulse, generated by impulsestressing of the crystals, drives the base voltage of transistor 40toward ground. This pulse is inverted through transistor 40 and appearsat the collec-.

tor as a positive pulse. The zener diode 34 holds the base of transistor40 at a positive 5 volt potential when a negative pulse is not present.Negative pulses are limited by the forward characteristics of diode 34which prevents reverse base-to-emitter (BVeb) breakdown of transistor 40by limiting the negative excursion at ground potential. v

The positive pulse at the collector of transistor 40 is then coupled bycapacitor 42 to the base of transistor 90 which is normally cut-off. Thecombination of capacitor 42 and resistor 52 acts as a pulse shapingnetwork. The positive pulse at transistor 90 will turn the transistor onif of adequate amplitude. A low impedance path-to-ground is therebysupplied through transistor 90, allowing capacitor 56 to .discharge. Thevoltage at pin 3 of quad inverter 14 switches sharply negative and cutsoff transistor 94.

A positive voltage from the collector of transistor 94 is then fed tothe base of transistor 92 (normally off) and turns it on. Transistor 92now acts as the current path-to-ground. The positive voltage from thecollector of transistor 94 is simultaneously fed to the differentiatorconsisting of capacitor 58 and resistor 60. The differentiator producesa positive pulse at the base of transistor 96 (normally on) and simplyturns transistor 96 on harder.

Meanwhile, capacitor 56 is charging at the time rate equal to t,. Ascapacitor 56 charges, the circuit remains in the quasi-state describedabove and the voltage at pin 3 of quad inverter 14 swings slowlypositive. When adequate base drive is achieved, transistor 94 turns on.The off time of transistor 94 is the circuit delay mechanism.

when transistor 94 switches on, transistor 92 switches off and thevoltage at pin 3 of quad inverter 14 returns immediately to its originalpositive state. The input transistor 90 will remain off due to theabsence of an input signal. This causes transistor 94 to saturate,producing a negative pulse out of the differentiator (capacitor 58 andresistor 60). The pulse cuts transistor 96 off and drives the collectorvoltage of transistor'96 positive. This output pulse is then coupled tothe SCR gate 72 through'diode 66, thus firing", the SCR 72. At thecompletion of the pulse. transistor 96 turns on and the entire circuitcycles back to its original state.

The output pulse width at pin 6 is determined by the differentiator(capacitor 58 and resistor 60) discharge time. This pulse is always ofadequate amplitude to fire the SCR 72.

Referring now to FIG. 4 which shows the sell" destruct portion 12 ofFIGS. l and 2. The circuit was designed to remove base drive voltagefrom transistor 96 upon reaching a reduced value of missile supplyvoltage 20. Asthe missile gas generator burns out, the missile turbogenerator slows down and causes a drop off in supply voltage 20. Thisvoltage reduction feature is used for missile self-destruct.

When the base drive voltage to transistor 96 is sufficiently reduced,the transistor cuts-off and produces a positive voltage at thecollector. This positive voltage is then coupled through diode 66 to theSCR gate 72. Theamplitude of this gate voltage is sufficient to causethe SCR 72 to fire over the designed temperature range. The couplingdiode 66 is necessaryto prevent the saturation of transistor 96 fromfiring the SCR 72' at elevated temperatures. Using the components listedabove, the operation of the self-destruct circuit 12 is as follows: withnormal supply voltage applied transistor 96 is on and saturated. As the25 volt supply 20 is lowered, transistor 96 starts out of saturation.When the supply is low enough the zener diode goes out of regulation andpasses very low current. The voltage drop across resistor becomesinsufficient to maintain transistor 96 on, therefore it shuts off. Thiscauses the collector voltage of transistor 96 to go positive and thusfire the SCR 72. The supply voltage reduction resistor 44 is such thatadequate voltage is left across zener diode 46 to produce, at minimum, al-volt pulse across the SCR gate 72. This circuit will produce an outputpulse at supply voltages of 9 12 volts, depending on tolerances andtemperatures. This represents a supply voltage reduction of at least 50percent.

Referring now to FIG. 5 which shows the target detection device firingcircuit 16 of FIGS. 1 and 2. The principle of the target detectiondevice (TDD) firing circuit is the same as in prior missile contact andselfdestruct circuits.

The main advantage of the circuit is the reduction of holding currentrequirements to a point that special SCR selection is no longernecessary. This was accomplished by increasing the value of resistor74and placing zener diode 64 across the SCR 72 and diode 70. During thecharging of capacitor 78, zener diode 64 acts as a high impedance, andthe charge path is through resistors 76, 74, and 80. Thetime required toreach a minimum charge of 24 volts is below the maximum specified designvalue. Therefore, the use of the large series resistance 74 wasjustified. This large resistancelowered the anode current of the SCR 72to a value which is below the SCR minimum holding current. The SCR gateresistor 68 was chosen as large as possible without jeopardizing theholding current requirements. Using the components listed above, theoperation of the TDD firing circuit is as follows: upon application ofthe TDD battery voltage 82 to the circuit, capacitor 78 starts to chargetoward a '33 volt final value. The SCR 72 is held off due to the lack ofsufficient gate voltage. The capacitor 78 will be charged to 24 volts(minimum) in less than 1.2 seconds.

A positive voltage pulse greater than 0.8 volts applied to the SCR gate72 will turn the SC R 72 on over all conditions. The SCR, in the onstate, acts as a low impedance path-to-ground and allows capacitor 78 todischarge through the SCR 72 and load attached to the output 84. Thisdischarge forms a negative voltage pulse across the load.

Supply voltage 20, in this embodiment. is the missile system filamentvoltage supply. Prior devices utilize the system gyro power supply 175VDC) as the supply voltage 20, resulting in possible misfire due tocircuit transients since the system gyro power is relativelyunregulated. By using the missile system filament voltage supply thesubject invention eliminates, or at least greatly reduces, the danger ofwarhead misfire since the filament voltage supply has better regulation.

What is claimed is: 1'. A fuze system for use in a projectile,comprising; first electrical means for providing a time delay after afirst predetermined event before an electrical signal is provided as anoutput, wherein said first predetermined event is the projectilescontact with a target, including an input from a source responsive tosaid contact, a quad inverter coupled to the input and providing a timedelayed output after the contact, and a time delay circuit coupled tosaid quad inverter for delaying the output of said quad inverter;

second electrical means for providing a time delay after a secondpredetermined event before an electrical signal is provided as anoutput; and

means for providing said electrical signal output after either saidfirst or said second predetermined event.

2. The system of claim 1 wherein .said second electrical means is ameans for detonating an explosive charge in said projectile at some timeafter said projectile's flight has been initiated.

3. The system of claim 1 wherein said time delay circuit comprises; aresistor and a capacitor.

4. The system of claim 1 wherein said first electrical means furtherincludes;

a crystal, which provides an electric pulse when impulse stressed suchas by impact, electrically con- Y nected to a one-shot multivibrator;

a one-shot multivibrator connected to said crystal for providing anelectric signal to said electrical signal output providing meansincluding said quad inverter; and wherein said electrical signal outputproviding means includes;

a firing circuit electrically connected to said multivibrator andtriggerable by said multivibrator for providing an electric signal tosaid explosive charge.

5. The system of claim 1 wherein said second electrical means includes;

an electric generator;

means for reducing the voltage output of said generator,

control means for providing :an electric signal to said electricalsignal output providing means when said generator voltage output isreduced; and wherein said electrical signal output providing meansincludes;

a firing circuit electrically connected to said control means andtriggerable by said control means for providing an electric signal tosaid explosive charge.

6. The system of claim 1 wherein said electrical signal output providingmeans includes a firing circuit electrically connected to saidquadinverter and triggerable by said quad inverter and electricallyconnected to said second electrical means and triggerable by said secondelectrical means.

7. The system of claim ll wherein said quad inverter includes first,second, third, and

fourth transistors and the base of said first transistor is effectivelycoupled to said input, the output terminal of said third transistor iscoupled to the base of said second transistor, and the output terminalsof said first and second transistors and the base of said thirdtransistor are coupled to said time delay circuit.

1. A fuze system for use in a projectile, comprising; first electricalmeans for providing a time delay after a first predetermined eventbefore an electrical signal is provided as an output, wherein said firstpredetermined event is the projectile''s contact with a target,including an input from a source responsive to said contact, a quadinverter coupled to the input and providing a time delayed output afterthe contact, and a time delay circuit coupled to said quad inverter fordelaying the output of said quad inverter; second electrical means forproviding a time delay after a second predetermined event before anelectrical signal is provided as an output; and means for providing saidelectrical signal output after either said first or said secondpredetermined event.
 2. The system of claim 1 wherein said secondelectrical means is a means for detonating an explosive charge in saidprojectile at some time after said projectile''s flight has beeninitiated.
 3. The system of claim 1 wherein said time delay circuitcomprises; a resistor and a capacitor.
 4. The system of claim 1 whereinsaid first electrical means further includes; a crystal, which providesan electric pulse when impulse stressed such as by impact, electricallyconnected to a one-shot multivibrator; a one-shot multivibratorconnectEd to said crystal for providing an electric signal to saidelectrical signal output providing means including said quad inverter;and wherein said electrical signal output providing means includes; afiring circuit electrically connected to said multivibrator andtriggerable by said multivibrator for providing an electric signal tosaid explosive charge.
 5. The system of claim 1 wherein said secondelectrical means includes; an electric generator, means for reducing thevoltage output of said generator, control means for providing anelectric signal to said electrical signal output providing means whensaid generator voltage output is reduced; and wherein said electricalsignal output providing means includes; a firing circuit electricallyconnected to said control means and triggerable by said control meansfor providing an electric signal to said explosive charge.
 6. The systemof claim 1 wherein said electrical signal output providing meansincludes a firing circuit electrically connected to said quad inverterand triggerable by said quad inverter and electrically connected to saidsecond electrical means and triggerable by said second electrical means.7. The system of claim 1 wherein said quad inverter includes first,second, third, and fourth transistors and the base of said firsttransistor is effectively coupled to said input, the output terminal ofsaid third transistor is coupled to the base of said second transistor,and the output terminals of said first and second transistors and thebase of said third transistor are coupled to said time delay circuit.